Oracle CPU-56T Manuel d'utilisateur Page 79
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PCI Bus B Devices’ Features and Data Paths
SPARC/CPU−56T 79
PCI Bus B
PCI bus B runs at 33 MHz and is 64 bit wide. It is the secondary PCI bus of the CPU board
and has the following devices attached to it:
S Ethernet controller
a
S Southbridge
S PCIO−2 controller
S PMC module
Ethernet Controller
The Ethernet controller used at PCI bus B is the same as is used at PCI bus A.a
Southbridge
The used Southbridge is an ALI M1535D+. It provides the following interfaces:
S Two IDE channels with ATA−100
S Parallel interface
S Floppy disk interface
S PS/2 keyboard/mouse interface
S SUN keyboard/mouse interface via two serial interfaces
PCIO−2 Controller
The used PCIO−2 controller is a SUN SME2300. It is a single−chip I/O subsystem using a
single PCI load and providing the following interfaces:
S Expansion bus (EBus) interface
S Four USB interfaces
S Media Independent Interface (MII)
EBus Interface
The PCIO−2 controller acts as EBus controller of the attached EBus. A description of all
devices attached to the EBus is given below.
a
- SPARC/CPU−56T 1
- Copyright 2
- Headquarters 3
- 4 SPARC/CPU−56T 4
- Contents 5
- 6 SPARC/CPU−56T 6
- 5 OpenBoot Firmware 7
- 6 Maps and Registers 8
- AppendixA Troubleshooting 9
- AppendixB Battery Exchange 9
- Product Error Report 10
- SPARC/CPU−56T 11 11
- 12 SPARC/CPU−56T 12
- SPARC/CPU−56T 13 13
- Using this Guide 14
- Abbreviations 15
- Revision History 17
- Other Sources of Information 19
- Safety Notes 20
- Installation 21
- Power Up 21
- Operation 21
- Replacement/Expansion 21
- RJ−45 Connector 22
- Environment 22
- Sicherheitshinweise 23
- Austausch/Erweiterung 25
- RJ−45 Stecker 25
- Batterie 25
- Umweltschutz 26
- Introduction 27
- Features 28
- Features Introduction 29
- SPARC/CPU−56T 29 29
- Figure 1: Function Blocks 29
- Standard Compliances 30
- Ordering Information 31
- 34 SPARC/CPU−56T 34
- Action Plan 35
- Requirements 36
- Power Requirements 37
- Hardware Accessories 38
- PMC Modules 39
- SPARC/CPU−56T 41 41
- 2. Remove voltage key 42
- Memory Modules 44
- Hard Disk 45
- SCSI−U160 Cable 45
- RS−422 Cable 45
- PS/2 Splitter Cable 45
- Switch Settings 46
- Board Installation 48
- Installing the CPU Board 49
- Removing the CPU Board 49
- Powering Up 50
- Installing Solaris 51
- Solaris Driver Package 52
- SPARC/CPU−56T 55 55
- 56 SPARC/CPU−56T 56
- Front Panel 57
- Connectors 59
- ETH1_RX+ 61
- 62 SPARC/CPU−56T 62
- On−Board Connectors 63
- Memory Module 64
- Its pinout is given below.a 65
- CPU Board 66
- SPARC/CPU−56T 67 67
- 68 SPARC/CPU−56T 68
- SPARC/CPU−56T 69 69
- 70 SPARC/CPU−56T 70
- SPARC/CPU−56T 71 71
- 72 SPARC/CPU−56T 72
- Block Diagram 73
- 74 SPARC/CPU−56T 74
- UltraSPARC IIi+ Processor 75
- Interrupt Controller 76
- PCI Bus A 77
- 78 SPARC/CPU−56T 78
- PCI Bus B 79
- SPARC/CPU−56T 81 81
- Real−Time Clock and NVRAM 84
- Serial Controller 84
- SPARC/CPU−56T 85 85
- PCI Bus C 86
- OpenBoot Firmware 87
- OpenBoot 90
- VxWorks Support 96
- NVRAM Boot Parameters 97
- Diagnostics 98
- Single Device 99
- Group of Devices 99
- IDE Devices 100
- Displaying System Information 101
- Resetting the System 103
- Activating OpenBoot Help 104
- Maps and Registers 106
- SPARC/CPU−56T 107 107
- Interrupt Map 108
- CPU Internal 109
- Physical Memory Map 110
- PCI Bus Address Map 111
- PCIO−2 Address Map 112
- Address: 1FF.F160.0100 116
- User LED Control Registers 117
- LED Control Register 2 118
- Address: 1FF.F160.0110 118
- LED Control Register 3 118
- Address: 1FF.F160.0112 119
- LED Control Register 4 119
- Address: 1FF.F160.0113 120
- Address: 1FF.F160.0120 120
- Watchdog Timer Registers 121
- Address: 1FF.F160.0130 122
- Address: 1FF.F160.0131 122
- Timer Registers 123
- Address: 1FF.F160.0144 125
- Interrupt Registers 127
- Address: 1FF.F160.0180 128
- Address: 1FF.F160.0184 128
- Reset Register 129
- Board Status Registers 130
- Address: 1FF.F160.01E1 131
- Address: 1FF.F160.01E2 132
- Hardware Revision Register 133
- I2C Registers 134
- Address: 1FF.F160.01FF 135
- Troubleshooting 136
- Error List 137
- Battery Exchange 139
- SPARC/CPU−56T 141 141
- 142 SPARC/CPU−56T 142
- SPARC/CPU−56T 143 143
- 144 SPARC/CPU−56T 144
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